It is required that a phase sync circuit used for the purpose of extracting a clock signal from an input data signal in a random NRZ format should continue outputting the clock signal while continuously maintaining the frequency of the clock signal without being influenced by the input data signal. For example, it is required that even in a case where a data signal having a large amount of noise in which pulse fluctuation with respect to time called jitter appears is input, or a case where a data signal such as one having a substantially long consecutive identical digits (CID) is input, the phase sync circuit should continue outputting the clock signal while constantly maintaining the frequency of the clock signal without being influenced by the input data signal. The random NRZ format is a pulse code format in which the pulse width is equal to the length of a code. If the clock signal is output with stability, it can be said that a shift of the frequency of the clock signal does not occur easily. On the contrary, in such a case, frequency acquisition to the desired condition cannot be easily performed. As a result, the capture range representing the frequency range in which phase synchronization can be performed in the phase sync circuit is necessarily reduced.
On the other hand, a voltage controlled oscillation circuit which is a component of the phase sync circuit has large variation in oscillation frequency due to its problem in terms of manufacture particularly in a case where it is implemented on an integrated circuit. If the oscillation frequency deviates largely from the bit rate of the input data signal in an initial state of the phase sync circuit due to this variation, phase synchronization is difficult since frequency adjustment cannot be easily performed. This phenomenon becomes more considerable if the above-mentioned capture range is reduced. Thus, there has been a problem that large variation cannot be tolerated in the oscillation frequency of the voltage controlled oscillation circuit in the phase sync circuit used for the purpose of extracting a clock signal because of the narrow capture range of the phase sync circuit.
A phase sync circuit having a dual-loop configuration has been frequently used to solve the above-described problem. FIG. 12 is a block diagram of a conventional phase sync circuit having a dual-loop configuration. In FIG. 12, symbol 80 denotes a conventional phase sync circuit, symbol 1 denotes a terminal through which a data signal D in a random NRZ format is input to the phase sync circuit 80; symbol 8 a terminal through which a reference lock signal RC having a frequency equal to a value obtained by dividing the bit rate of the data signal D input through the terminal 1 by a frequency division ratio N of a frequency dividing circuit 84 (described below) is input; symbol 81 a phase comparison circuit which performs phase comparison between the data signal D in the random NRZ format input through the terminal 1 and a clock signal CK output from a voltage controlled oscillation circuit 83 (described below); symbol 85 a frequency comparison circuit which performs frequency comparison between an output clock signal from a frequency dividing circuit 84 (described below) and the reference clock signal RC input through the terminal 8; symbol 82 a low-pass filter to which both a phase comparison result obtained by the phase comparison circuit 81 and a frequency comparison result obtained by the frequency comparison circuit 85 are input, and which outputs a direct-current component; symbol 83 the voltage controlled oscillation circuit which controls the oscillation frequency by the output signal from the low-pass filter 82; symbol 84 the frequency dividing circuit which divides by N the output clock signal CK from the voltage controlled oscillation circuit 83; and symbol 2 a terminal which is an output terminal of the voltage controlled oscillation circuit 83, and through which the clock signal CK extracted by the phase sync circuit 80 from the data signal D input through the terminal 1 is output.
As shown in FIG. 12, the phase sync circuit 80 has two loops, i.e., a phase comparison loop P formed by three circuits: the phase comparison circuit 81, the low-pass filter 82 and the voltage controlled oscillation circuit 83, and a frequency comparison loop F formed by four circuits: the frequency comparison circuit 85, the low-pass filter 82, the voltage controlled oscillation circuit 83 and the frequency dividing circuit 84. The phase comparison loop P is a loop for phase synchronization of the output clock signal CK from the voltage controlled oscillation circuit 83 with the data signal D in the random NRZ format input through the terminal 1. Through the loop P, the clock signal CK is extracted as high-quality clock signal from the input data signal D. On the other hand, the frequency comparison loop F functions in a case where phase synchronization cannot be easily performed only with the phase comparison loop P because of the narrow capture range of the same, particularly in a case where the oscillation frequency of the voltage controlled oscillation circuit 83 deviates largely from the bit rate of the data signal D input through the terminal, for example, in an initial state immediately after powering on. That is, the frequency comparison loop F is introduced for the purpose of ensuring normal phase synchronization with the phase comparison loop P by bringing the oscillation frequency of the voltage controlled oscillation circuit 83 close to the bit rate of the input data signal D.
The phase sync circuit 80 having the above-described dual-loop configuration is a circuit capable of achieving equivalent broadening of the capture range of the phase sync circuit 80 as well as extraction of the high-quality clock signal CK by using the frequency comparison loop F in addition to the phase comparison loop P for extracting the clock signal CK from the data signal D in the random NRZ format. However, high frequency precision is required of the reference clock signal RC necessary for the frequency comparison loop F for a reason relating to the role of the reference clock signal RC. Therefore, it has been impossible to form the oscillation circuit for generating the reference clock signal RC in an integrated circuit. There is, therefore, a need for an external circuit and there is a problem that a considerable drawback in terms of convenience and cost exists.